Implementation of Modified Booth Recoded Wallace Tree Multiplier for fast Arithmetic Circuits

Power consumption has become a critical concern in today’s VLSI system design. The growing market for fast floating-point co-processors, digital signal processing chips, and graphics processor has created a demand for high speed, area-efficient multipliers. The Modified Booth Recoding method is widely used to generate the partial products for implementation of large parallel multipliers, which adopts the parallel encoding scheme. A Wallace tree multiplier is an improved version of tree based multiplier architecture and uses carry saveaddition algorithm to reduce the latency. This paper presents efficient design of multiplier that combines the features of Wallace tree and Modified Booth algorithm, and aimed at reduction of area and improvement in speed.An efficient VerilogHDL code has been written, successfully simulated and synthesized for Xilinx FPGA vertex-6 low power (Xc6vlx75tl-1Lff484) device, using Xilinx 12.2 ISE and XST. The analyses obtained from implementation show that architecture is 41% faster than the Wallace tree architecture with optimal area utilization. Keywords—Multiplier, Adder, Modified booth recoding, Wallace tree, Xilinx.